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1 ltc1650 low glitch 16-bit voltage output dac the ltc ? 1650 is a deglitched rail-to-rail voltage output 16-bit digital-to-analog converter (dac) available in a 16-pin narrow so package. it has 16-bit monotonicity over temperature and includes a rail-to-rail output buffer amplifier and an easy to use three-wire cascadable serial interface. the ltc1650 operates with dual 5v supplies. with reflo = 0v and refhi = v ref , the output will swing from 0v to v ref in unipolar mode or v ref in bipolar mode. the ltc1650 has excellent accuracy over its full operating temperature range along with very low power dissipation of 50mw with dual 5v supplies. this, along with the small outline package, makes it the most flexible high resolution digital-to-analog converter available today. the ltc1650 has a fast settling time of 4 m s to 16 bits and a low midscale glitch of under 2nv-s. this makes the ltc1650 ideal for waveform generation or other applica- tions where output dynamic performance is important. + 16-bit dac 16-bit dac register 16-bit shift register power-on reset supply sense clr v rst av dd 5v rstout v out uni/bip reflo dgnd 1650 ta01 10 8 7 5 6 12,13 4.096v 5v ?v cs/ld clk d in d out refhi 11 15 9 2 1 16 4 av ss 14 dv dd 3 code 0 1.0 dnl error (lsb) 0.8 0.4 0.2 0 1.0 0.4 16384 32768 1650 ta02 0.6 0.6 0.8 0.2 49152 65535 differential nonlinearity vs input code n 16-bit monotonic over temperature n low glitch impulse: 2nv-s n low noise: 30nv/ ? hz n buffered rail-to-rail voltage output n low power: 50mw from 5v supplies n unipolar or bipolar output (0v to v ref or v ref ) n 4-quadrant multiplying capability n asynchronous clear to user-defined voltage n power-on reset n three-wire spi and microwire tm compatible serial interface n schmitt trigger on clk input allows direct optocoupler interface n 16-pin narrow so package n industrial process control n precision industrial equipment n waveform generation n automatic test equipment n high resolution offset and gain adjustment , ltc and lt are registered trademarks of linear technology corporation. microwire is a trademark of national semiconductor corporation. features descriptio u applicatio s u typical applicatio u
2 ltc1650 the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. av dd = 4.75v to 5.25v, av ss = C 4.75v to C 5.25v, dv dd = 4.75v to 5.25v, reflo = 0v, refhi = 4.096v, v out unloaded, unless otherwise noted. (note 1) av dd , dv dd to dgnd .............................. C 0.5v to 7.5v ttl input voltage .................................... C 0.5v to 7.5v v out , v rst ................................ C 0.5v to (av dd + 0.5v) av ss .........................................................0.5v to C 7.5v operating temperature range ltc1650c .............................................. 0 c to 70 c ltc1650i ............................................ C 40 c to 85 c maximum junction temperature ......................... 125 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec)................. 300 c order part number top view s package 16-lead plastic so n package 16-lead pdip 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v out v rst dv dd dgnd d in d out clk cs/ld uni/bip av dd av ss reflo s reflo f refhi rstout clr t jmax = 125 c, q ja = 85 c/ w (n) t jmax = 125 c, q ja = 130 c/ w (s) ltc1650acn ltc1650ain ltc1650acs ltc1650ais ltc1650cn ltc1650in ltc1650cs ltc1650is ltc1650cs/cn ltc1650acs/acn ltc1650is/in ltc1650ais/ain symbol parameter conditions min typ max min typ max units dac characteristics, unipolar/bipolar output unless otherwise noted resolution l 16 16 bits monotonicity l 16 16 bits dnl differential nonlinearity guaranteed monotonic (note 2) l 0.15 0.9 0.15 0.5 lsb inl integral nonlinearity integral nonlinearity (note 2) l 4 16 4 8 lsb bipolar zero error t a = 25 c 5 12 5 12 lsb bipolar zero error t a = t min to t max l 18 18 lsb v os unipolar offset error t a = t min to t max l 0.5 12 0.5 12 lsb v os tc offset error temperature 0.5 0.5 m v/ c coefficient gain error t a = t min to t max l 4 18 4 12 lsb gain error temperature 0.5 0.5 ppm/ c coefficient bipolar negative t a = t min to t max l 1 16 1 12 lsb full-scale error see definitions section bipolar negative see definitions section 0.75 0.75 ppm/ c full-scale error tempco consult ltc marketing for parts specified with wider operating temperature ranges. absolute axi u rati gs w ww u package/order i for atio uu w electrical characteristics
3 ltc1650 the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. av dd = 4.75v to 5.25v, av ss = C 4.75v to C 5.25v, dv dd = 4.75v to 5.25v, reflo = 0v, refhi = 4.096v, v out unloaded, unless otherwise noted. symbol parameter conditions min typ max units power supply characteristics av dd positive supply voltage l 4.75 5.0 5.25 v dv dd positive supply voltage l 4.75 5.0 5.25 v av ss negative supply voltage l C 4.75 C 5.0 C 5.25 v i avdd av dd supply current 4.75v av dd 5.25v (note 5) l 5 7.5 ma i avss av ss supply current C 5.25v av ss C 4.75v (note 5) l C 7.5 C 5 ma i dvdd dv dd supply current 4.75v dv dd 5.25v (note 5) l 0.1 0.25 ma psrr av dd , dv dd supply rejection 4.75v av dd , dv dd 5.25v l 0.5 1.5 lsb/v av ss supply rejection C 5.25v av ss C 4.75v l 0.5 1.5 lsb/v reference input r in reference input resistance l 2.5 5 7.5 k w refhi range l C 4.0 4.0 4.5 v reflo range l C 1.0 0 1.0 v op amp dc performance short-circuit current low v out shorted to gnd l 25 50 ma short-circuit current high v out shorted to v cc l 25 50 ma output impedance measured at midscale 0.15 w dac output range unipolar mode (note 9) 0v to v ref v bipolar mode (note 9) v ref v ac performance voltage output slew rate l 0.8 2.0 v/ m s voltage output settling time unloaded (note 4) 4 m s midscale glitch impulse 1.8 nv-s digital feedthrough 0.05 nv-s output noise voltage density 1khz to 100khz (note 6) 30 nv/ ? hz sinad signal-to-noise + distortion ratio refhi = 1khz 4v p-p 96 db electrical characteristics
4 ltc1650 the l denotes specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. av dd = 4.75v to 5.25v, av ss = C 4.75v to C 5.25v, dv dd = 4.75v to 5.25v, reflo = 0v, refhi = 4.096v, v out unloaded, unless otherwise noted. note 5: digital inputs at 0v or dv dd . note 6: measured at v out . refhi = reflo = 0v, unipolar mode. note 7: when part powers up or when it is reset, the output is connected to v rst through this switch. note 8: reset is active when any supply goes below this threshold. note 9: reflo = 0v, refhi = v ref . for reflo 1 0v see operation section. note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: nonlinearity is defined from code 0 to code 65535 (full scale) (end point inl, see definitions section). note 3: guaranteed by design. not subject to test. note 4: to 1lsb. unipolar mode. dac switched between all 1s and all 0s. symbol parameter conditions min typ max units digital i/o characteristics v ih digital input high voltage l 2.4 v v il digital input low voltage l 0.8 v v oh digital output high voltage i out = C1ma, d out only l v cc C 1.0 v v ol digital output low voltage i out = 1ma, d out only l 0.4 v i lk digital input leakage v in = gnd to v cc l 10 m a c in digital input capacitance (note 3) 10 pf reset characteristics r on v out and v rst switch resistance v rst = 0.5v (note 7) l 200 500 w threshold voltage for reset av dd or dv dd (note 8) l 1.5 2.5 3.2 v ? av ss ? (note 8) l 1.5 2.5 3.2 v switching characteristics t 1 d in valid to clk setup l 40 ns t 2 d in valid to clk hold l 0ns t 3 clk high time (note 3) l 40 ns t 4 clk low time (note 3) l 40 ns t 5 cs/ld pulse width (note 3) l 50 ns t 6 lsb clk to cs/ld (note 3) l 40 ns t 7 cs/ld low to clk (note 3) l 20 ns t 8 d out output delay c load = 100pf l 5 45 150 ns t 9 clk low to cs/ld low (note 3) l 20 ns t 10 clr pulse width l 50 ns electrical characteristics
5 ltc1650 typical perfor a ce characteristics uw integral nonlinearity (inl) vs input code code 0 16384 32768 49152 65535 inl error (lsb) 1650 g01 5 4 3 2 1 0 ? ? ? ? ? 1 s/div 1650 g03 cs/ld 5v/div 4.096v 0v v out 1v/div code 0 16384 32768 49152 65535 dnl error (lsb) 1650 g02 1.0 0.8 0.6 0.4 0.2 0 0.2 0.4 0.6 0.8 1.0
6 ltc1650 dv dd supply current vs temperature offset error vs temperature typical perfor a ce characteristics uw temperature ( c) 55 35 15 5 25 45 65 85 105 125 supply current (ma) 1650 g10 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 temperature ( c) 55 35 15 5 25 45 65 85 105 125 supply current ( a) 1650 g11 25 20 15 10 5 0 temperature ( c) offset error (lsb) 1650 g12 0 ?.5 ?.0 ?.5 ?.0 55 ?5 5 35 65 95 125 av ss supply current vs temperature supply current vs logic input voltage gain error vs temperature logic input voltage (v) 012345 d vdd supply current (ma) 1650 g14 2 1 0 all logic inputs tied together temperature ( c) 55 ?5 5 35 65 95 125 gain error (lsb) 1650 g13 0 ? ? ? ? ? ? ? ? ? ?0 v out (pin 1): the dac output. the output will swing from reflo to refhi in unipolar mode and from (2 ? reflo C refhi) to refhi in bipolar mode. v rst (pin 2): the user-defined voltage to which the output gets reset when clr is active, when any of the supplies drop below 2.5v or when the part powers-up. the output will stay at this voltage until a new code is loaded into the dac register. dv dd (pin 3): the digital positive supply input. 4.75v dv dd 5.25v. dgnd (pin 4): digital ground. d in (pin 5): the ttl level input for the serial interface data. data on the d in pin is latched into the shift register on the rising edge of the serial clock. data is loaded as one 16-bit word, msb first. d out (pin 6): the output of the shift register that be- comes valid on the rising edge of the serial clock. clk (pin 7): the ttl level input for the serial interface clock. uu u pi fu ctio s
7 ltc1650 cs/ld (pin 8): the ttl level input for the serial interface enable and load control. when cs/ld is low, the clk signal is enabled so the data can be clocked in. when cs/ld is pulled high, data is loaded from the shift register into the dac register, updating the dac output. clr (pin 9): the dac is cleared to v rst when this pin is pulled low. it should be logic high for normal operation. rstout (pin 10): the logic output pin that goes active when any of the supplies drop below 2.5v. this pin is active low. refhi (pin 11): the reference input pin. the dac is capable of 4-quadrant multiplying; this pin can swing from 4.5v to C 4v. reflo f/reflo s (pins 12, 13): the force and sense pin for the lower reference input. this should nominally be tied to ground. this pin can swing from C 1v to 1v. av ss (pin 14): the analog negative supply input. C 5.25v av ss C 4.75v. requires a bypass capacitor to ground. av dd (pin 15): the analog positive supply input. 4.75v av dd 5.25v. requires a bypass capacitor to ground. uni/bip (pin 16): the unipolar/bipolar selection pin. for unipolar operation, tie this pin to v out and for bipolar operation, tie this pin the refhi. clk t 1 d in cs/ld d out b14 b15 b14 b13 b1 b0 lsb b15 msb b13 b0 b1 1650 td (previous word) t 9 t 8 t 6 t 7 t 4 t 3 t 5 t 2 uu u pi fu ctio s ti i g diagra u ww
8 ltc1650 defi n itio n s uu resolution (n) resolution is defined as the number of digital input bits, n. it defines the number of dac output states (2 n ) that divide the full-scale range. the resolution does not imply linearity. full-scale voltage (v fs ) this is the output of the dac when all bits are set to 1. the output will swing from reflo to refhi in unipolar mode and from (2 ? reflo C refhi) to refhi when in bipolar mode. voltage offset error (v os ) this is the voltage at the output when the dac is loaded with all zeros. least significant bit (lsb) one lsb is the ideal voltage difference between two successive codes. lsb = (v fs C v os )/(2 n C 1) = (v fs C v os )/65535 integral nonlinearity (inl) endpoint inl is the maximum deviation from a straight line passing through the endpoints of the dac transfer curve. it is measured after adjusting out gain and offset error for the dac. differential nonlinearity (dnl) dnl is the difference between the measured change and the ideal 1lsb change between any two adjacent codes. the dnl error between any two codes is calculated as follows: dnl = ( d v out C lsb)/lsb d v out = the measured voltage difference between two adjacent codes. gain error (ge) gain error is the difference between the full-scale output of a dac from its ideal full-scale value after offset error has been adjusted for. bipolar zero error when configured for bipolar output and with reflo tied to 0v, the ltc1650 output should be 0v with (10000) loaded in. any deviation from 0v at this code is called bipolar zero error. bipolar negative full-scale error this is the offset error of the ltc1650 in bipolar mode.
9 ltc1650 serial interface the data on the d in input is loaded into the shift register on the rising edge of the clock. data is loaded as one 16-bit word, msb first. the dac register loads the data from the shift register when cs/ld is pulled high. the clock is disabled internally when cs/ld is high. note: clk must be low before cs/ld is pulled low to avoid an extra internal clock pulse. the buffered output of the 16-bit shift register is available on the d out pin which swings from dgnd to dv dd . multiple ltc1650s may be daisy-chained together by connecting the d out pin to the d in pin of the next chip while the clock and cs/ld signals remain common to all chips in the daisy chain. the serial data is clocked to all of the chips, then the cs/ld signal is pulled high to update all of them simultaneously. when clr is pulled low or when the part powers up, the output connects through an internal pass gate to v rst and will go to whatever voltage is on v rst . when any of three supplies (dv dd , av dd , |av ss |) goes below 2.5v, the rstout pin goes low and stays low as long as the supply is below 2.5v. the power-on reset is also activated when one of the supplies drops below 2.5v and the output is then connected to v rst . the output connects to v rst when any of three conditions occur: clr goes low, the part powers up or one of the supplies drops below 2.5v. this condition exists as long as cs/ld is low. as soon as cs/ld goes high, the dac register is loaded with the data in the shift register and the output will settle to its new value. voltage output the ltc1650 rail-to-rail buffered output can source or sink 5ma over the entire operating temperature range. the output is specified to swing up to 4.5v on 4.75v supplies with v out unloaded. (for typical output swing at various load currents, refer to the typical curve minimum supply headroom for full output swing vs load cur- rent.) the buffer amplifier can drive 1000pf without going into oscillation. the ltc1650 has a deglitched voltage output. the midscale glitch is less than 2nv-s. the digital feedthrough is about 0.05nv-s. output ranges the ltc1650 is capable of unipolar or bipolar output swing. when the uni/bip pin is connected to v out the part is configured for unipolar operation and the output will swing from reflo to refhi. when uni/bip is connected to refhi the part is configured in bipolar mode and the output will swing from (2 ? reflo C refhi) to refhi and will be at reflo at midscale. with reflo = 0v the output swing is refhi in bipolar mode and 0v to refhi in unipolar mode. operatio u
10 ltc1650 typical applicatio u 16-bit industrial process controller ?v 0.1 f p control voltage 0v to 4.5v (69 v/lsb) 5v 5v clk d in cs/ld clr rstout d out v out 1650 ta03 ltc1650 refhi av dd dv dd uni/bip reflo f/s dgnd av ss v rst in lt1019-4.5 4.5v 6v to 30v 0.1 f 0.1 f
11 ltc1650 package descriptio n u information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. n package 16-lead pdip (narrow .300 inch) (reference ltc dwg # 05-08-1510) s package 16-lead plastic small outline (narrow .150 inch) (reference ltc dwg # 05-08-1610) n16 1098 0.255 0.015* (6.477 0.381) 0.770* (19.558) max 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0.020 (0.508) min 0.125 (3.175) min 0.130 0.005 (3.302 0.127) 0.065 (1.651) typ 0.045 ?0.065 (1.143 ?1.651) 0.018 0.003 (0.457 0.076) 0.100 (2.54) bsc 0.009 ?0.015 (0.229 ?0.381) 0.300 ?0.325 (7.620 ?8.255) 0.325 +0.035 0.015 +0.889 0.381 8.255 () *these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch (0.254mm) 0.016 ?0.050 (0.406 ?1.270) 0.010 ?0.020 (0.254 ?0.508) 45 0 ?8 typ 0.008 ?0.010 (0.203 ?0.254) 1 2 3 4 5 6 7 8 0.150 ?0.157** (3.810 ?3.988) 16 15 14 13 0.386 ?0.394* (9.804 ?10.008) 0.228 ?0.244 (5.791 ?6.197) 12 11 10 9 s16 1098 0.053 ?0.069 (1.346 ?1.752) 0.014 ?0.019 (0.355 ?0.483) typ 0.004 ?0.010 (0.101 ?0.254) 0.050 (1.270) bsc dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * **
12 ltc1650 ? linear technology corporation 1998 1650fa lt/tp 1001 1.5k rev a ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com related parts typical applicatio u a 10v bipolar output 16-bit dac ?v 0.1 f p 0v to 10v (unipolar mode) 10v to 10v (bipolar mode) bipolar unipolar 5v 5v 15v 15v clk d in cs/ld clr rstout v out 1650 ta04 ltc1650 refhi av dd dv dd uni/bip reflo dgnd av ss v rst in out in lt1019-4.5 15v 0.1 f + lt1468 90k 110k 10pf 0.1 f part number description comments dacs ltc1257 single 12-bit v out dac, full scale: 2.048v, v cc : 4.75v to 15.75v, 5v to 15v single supply, complete v out dac in reference can be overdriven up to 12v, i.e., fs max = 12v so-8 package ltc1446/ltc1446l dual 12-bit v out dacs in so-8 package ltc1446: v cc = 4.5v to 5.5v, v out = 0v to 4.095v ltc1446l: v cc = 2.7v to 5.5v, v out = 0v to 2.5v ltc1448 dual 12-bit v out dac, v cc : 2.7v to 5.5v output swings from gnd to ref. ref input can be tied to v cc ltc1450/ltc1450l single 12-bit v out dacs with parallel interface ltc1450: v cc = 4.5v to 5.5v, v out = 0v to 4.095v ltc1450l: v cc = 2.7v to 5.5v, v out = 0v to 2.5v ltc1451/ltc1452/ single 12-bit v out dacs with serial interface ltc1451: v cc = 4.5v to 5.5v, v out = 0v to 4.095v ltc1453 ltc1452: v cc = 2.7v to 5.5v, v out = 0v to 2 ? v ref ltc1453: v cc = 2.7v to 5.5v, v out = 0v to 2.5v ltc1456 single rail-to-rail output 12-bit dac with clear pin, low power, complete v out dac in so-8 full scale: 4.095v, v cc : 4.5v to 5.5v package with clear pin ltc1458/ltc1458l quad 12 bit rail-to-rail output dacs with added functionality ltc1458: v cc = 4.5v to 5.5v, v out = 0v to 4.095v ltc1458l: v cc = 2.7v to 5.5v, v out = 0v to 2.5v ltc1595/ltc1596 16-bit serial i/o multiplying i out dacs 1lsb max inl/dnl, low glitch, so-8 package (ltc1595), clear pin (ltc1596) ltc1659 single rail-to-rail 12-bit v out dac in msop-8 package, low power multiplying v out dac in msop-8 package. v cc : 2.7v to 5.5v output swings from gnd to ref. ref input can be tied to v cc references lt1019 precision voltage reference ultralow drift 5ppm/ c, initial accuracy: 0.05% lt1634 micropower precision reference low drift 10ppm/ c, initial accuracy: 0.05%

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